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RTL8801-ver. k datasheet 2002,7,1 1 RTL8801 phy/ieee 1394a 3 port 100/200/400 mb/s cable transceiver/arbiter chip 1. features fully support provisions of ieee1394-1995 for high- performance serial bus and the p1394a draft 2.0 standard provides three fully compliant cables ports at 100/200/400 mbits/s and available with three ports fully compliant with open hci requirements full p1394a additional function support support optional 1394 annex j electrical isolation barrier at phy-link interface support power-down feature to conserve energy in battery ? powered applications cable power presence monitoring separate cable bias (tpbias) and driver termination voltage supply for each port encode and decode functions included for data-strobe bit level encoding support lps/link-on pin for phy-link interface incoming data resynchronized to local clock single 24.576 mhz crystal provide transmit/receive data at 100/200/400 mbits/s and llc clock at 49.152 mhz node power-class information signaling for system power management adaptive equalizer easy configured as a repeater single 3.3v power supply 64 pin lqfp package 2. general description the RTL8801 provides three-port physical layer(phy) function in a cable-based ieee 1394-1995 and ieee p1394a network. each cable port incorporates two differential line transceivers. the transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. data bits to be transmitted through the cable ports are received from the link on 2/4/8 data lines (d0-d8), and are latched internally in the RTL8801 in synchronization with the 49.152 mhz system clock these bits are combined serially, encoded, and transmitted at 98.304 , 196.608 or 393.216mbps as the outbound data-strobe information stream. during transmission, the encoded www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 2 data transmitted differential on the tpb cable pair(s), and the encoded strobe information is transmitted differentially on the tpa cable pair(s). during packet reception the tpa and tpb transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. the encoded data information is received on the tpa cable pair, and the encoded strobe information is received on the tpb cable pair. the received data- strobe information is decoded to recover the received clock signal and the serial data bits. the serial data bits are split into two or four parallel transmitted (repeated) out of the other active (connected) cable ports. both the tpa and tpb cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. the output of these comparators are used by the internal logic to determine the arbitration status. the tpa channel monitors the incoming cable common- mode voltage. the value of this common mode voltage is used during arbitration to set the speed of the next packet transmission. in addition, the tpb channel monitors the incoming cable common- mode voltage for the presence of the remotely supplied twisted-pair bias voltage. the presence or absence of this common-mode voltage is used as an indication of cable connection status. the cable connection status signal is internally debounced in the RTL8801 on a cable disconnect-to-connect. the debounced cable connection status signal initiates a bus reset. on a cable disconnect-to-connect a debounce delay is incorporated. there is no delay on a cable disconnect. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 3 3. pin assignment RTL8801 lreq dvss ctl0 ctl1 d0 d1 dvdd d3 d4 d5 d6 d7 dvss lact lps d2 dvdd lkon/c pdisable pc0 pc1 pc2 iso\ dxvss dxvdd test2 test1 agnd tvdd rvdd rgnd cps tpbias3 tpa3+ tpa3- tpb3+ tpb3- pvdd tpbias2 tpa2- tpb2+ tpb2- tpbias1 tpa1+ tpa1- tpb1+ tpb1- tpa2+ dvss sclk dvdd reset\ xo xi adgnd pllgnd btset bgnd tgnd pllgnd pllvdd bvdd pgnd advdd www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 4 4. pin descriptions symbol type pin(s) no. description c/lkon i/o 18 (input) bus manager capable. when set as input, c/lkon specifies in the self-id packet that the node is bus manager capable. (output) link on. when set as an output, c/lkon indicates the reception of a link-on packet by asserting a 6.114 mhz square wave signal. cna o 15 cna is asserted high when none of the phy ports are connected to another active port. this circuit remains acitve during the power down mode. cps i 24 cable power status. cps is normally connected to the cable power through a 400-kohm resistor. this circuit drivers an internal comparator that detects the presence of cable power. lps i 16 link power status. lps is connected to either the vdd supplying the link or to a pulsed output that is active when the link is powered for the purpose of monitoring the link power status. lreq i 1 link request. lreq is an input from the link that requests the phy to perform some service. lact\iso i 23 link active. this pin direct the phy with link or not ctl0 ctl1 i/o 3,4 control i/o. the ctln pins are bi-directional communications control signals between the phy and llc. d0-d7 i/o 5,6,8,9,10,11, 12,13 data i/o. the d terminals are bi-directional and pass data between the phy and llc. sysclk o 63 system clock. sysclk provides a 49.152 mhz clock signal, which is synchronized with the data transfers to the llc. tpa1+ tpa1- i/o 36,35 port1, cable pair a. tpa1 is the port a connection to the twisted-pair cable .board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. tpa2+ tpa2- i/o 41,40 port2, cable pair a. tpa3 is the port a connection to the twisted-pair cable .board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector . tpa3+ tpa3- i/o 47,46 port2, cable pair a. tpa3 is the port a connection to the twisted-pair cable .board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. tpb1+ tpb1- i/o 34,33 port1, cable pair b. tpb1 is the port b connection to the twisted-pair cable .board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. tpb2+ tpb2- i/o 39,38 port2 , cable pair b. tpb2 is the port b connection to the twisted-pair cable .board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resis tors and to the cable connector. tpb3+ tpb3- i/o 45,44 port3, cable pair b. tpb3 is the port b connection to the twisted-pair cable .board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. tpbias1 tpbias2 tpbias3 o 37,42,48 portn, twisted pair bias. it provides the 1.86-v nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. pc0-pc2 i 20,21,22 power class indicator. the pc signals set the bit values of the three power class bits in self-id packet . these bits can be programed by www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 5 tying the terminals to vdd or gnd. xi xo 59,60 crystal oscillator input and output. pllgnd - 52,56 pll circuit ground. the pin should be tied together to the low impedance ground plane pllvdd - 51 pll circuit power. pllvdd supplies power to the pll circuit avdd - 30,31,43,50 analog power. avdd supplies power to the analog port of the device. avss - 32,49,53,54 analog ground. these pins should be tied together to the low impedance ground plane. btset i 55 current setting resistor input. this pin is connected to an external resistor to set the internal operating current and cable driver output current. pdisable i 19 port configuration monitor input. this pin is only active in power on stage and meets the requirement of ohci. dvdd - 7,17,26,57,62 digital power. dvdd supplies power to the digital part of the device. dvss - 2,14,25,29,58 ,64 digital ground. these pins should be tied together to the low impedance ground plane. reset\ i 61 reset. an external capacitor is required for proper power-up operation. test1 i 28 test control pin. this pin is used in the manufacturing test of the device. for normal use it should be tied to dvss. test2 i 27 test control pin. this pin is used in the manufacturing test of the device. for normal use it should be tied to dvdd. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 6 5. functional block diagram bias voltage and current generator link interfac e i/o cps lps iso\ sys clk lreq ctl0 ctl1 d0 d1 d2 d3 received data decoder/ retimer arbitration and control state machine logic transmit data encoder pc0 pc1 pc2 c/lkon testm2 testm1 reset\ cable port 1 cable port 2 cable port 3 crystal oscillator, pll system, and clock generator tpbias3 tpbias2 tpbias1 tpa1+ tpa1- tpb1+ tpb1- tpa2+ tpa2- tpb2+ tpb2- tpa3+ tpa3- tpb3+ tpb3- xi xo d5 d4 d6 d7 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 7 6. functional description the operation of the cable phy can best be understood with reference to the 5.0 block diagram show before. the main controller of the cable phy is the block labeled ? arbitration and control state machine logic ? which responds to arbitration requests from the link layer and changes in the state of attached ports. it provides the management and timing signals for transmitting, receiving, and repeating packets. it also provides the bus reset and configuration . the cable environment supports the immediate, fair, isochronous, and cycle_master arbitration classes, where the cycle_master class is only available at the root node. cable arbitration has two parts: a three-phase initialization process (bus reset, tree identify, and self- identify), and a normal operation phase. each of these four phases is described using a state machine, the state machine and the list of actions and conditions are the normative part of ieee standard. the ? receive data decoder/retimer ? block decodes the data-strobe signal and retimes the received data to a local fixed-frequency clock provided by the local clock. since the clocks of receiving and transmitting nodes can be up to 100 ppm different from the nominal, the data resynch function has to be able to compensate for a difference of 200 ppm over the maximum packet length of 84.31 us (1024 byte isochronous packet at 98.304 mbit/s). data reception for the cable environment physical layer has three major functions: decoding the data-strobe signal to recover a clock, synchronizing the data to a local clock for use by the link layer, repeating the synchronized data out all other connected ports. the ? transmit data encoder ? block provides a common interface to the link layer for both packet daa and arbitration signal (gaps and bus reset indicators). data transmission is a straightforward function: the data bits are sent to the attached peer phy along with the appropriately encoded strobe signal using the timing provided by the phy transmit clock. if connected port cannot accept data at the requested speed, then no data is send (leaving the drivers in the ? 01 ? data prefix condition). the ? link interface ? block provides a scalable, cost-effective method to connect one serial bus link chip to one serial bus phy chip. the width of the data bus scales with the highest speed both chips can support, using two pins per 100 mbit/s. the clock rate of the signals at this interface remains constant, independent of speed, to support galvanic isolation for implementations where it is www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 8 desirable. the phy has control over the bidirectional pins. the link only drives these pins when control is transferred to it by the phy. the link performs all unsolicited activity through a dedicated request pin. the possible actions that may occur on the interface are categorized as transmit, receive, status, and request. 7. register definitions definitions and usage for each of the registers listed below are provided on this and the following pages: 7.1 phy register map for the cable environment address 0 1 2 3 4 5 6 7 0000b physical_id r ps 0001b rhb ibr gap_count 0010b extended(7) reserved total_ports 0011b max_speed reserved delay 0100b link_ac tive contend er jitter pwr_class 0101b resume _int isbr loop pwr_fail timeout port_ev ent enab_ac cel enab_m ulti 0110b reserved 0111b page_select reserve port_select 1000b register0(page_select) 1111b register7(page_select) www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 9 7.2 phy register fields for the cable environment size type power reset value description physical_id 6 r - the address of this node determined during self-identification. a value of 63 indicates a malconfigured bus; the link shall not transmit any packets. r 1 r - when set to one, indicate that this node is the root. ps 1 r - cable power status. rhb 1 rw 0 root hold-off bit. when set to one, instructs the phy to attempt to become the root during the next tree identify process. ibr 1 rw 0 initiate bus reset. when set to one, instructs the phy to initiate a bus reset immediately (without arbitration). this bit causes assertion of the reset state for 166 us and is self-clearing. gap_count 6 rw 3f used to configure the arbitration timer setting in order to optimize gap times according to the topology of the bus. ieee 1394-1995 4.3.6 extended 3 r 7 constant value of seven total_ports 5 r 3 the number of ports implemented by this phy max_speed 3 r 010 indicates the maximum speed this phy supports; 000 - 98.304 mbit/s 001 - 98.304 and 196.608 mbit/s 010 ? 98.304, 196.608 and 393.216 mbit/s 011 - .98.304, 196.608, 393.216 and 786.43 mbit/s 100 ? 98. 304, 196.608, 393.216, 786.43 and 1,572.864 mbit/s 101 ? 98. 304, 196.608, 393.216, 786.43, 1,572,864 and 3,145.728 mbit/s all other values are reserved for future definition delay 4 r 0 worse case repeater delay, expressed as 144+(delay*20)ns. link_active 1 rw 1 link enabled. default value of one subsequent to a power reset. otherwise cleared or set by software to control the value of the l bit transmitted in the self-id packet. the transmitted l bit shall be the logical and of this bit and the lps signal. contender 1 rw pin c/lk on contender. cleared or set by software to control the value of the c bit transmitted in the self-id packet. www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 10 pwr_class 3 rw pin pc0- pc2 power class. controls the value of the pwr field transmitted in the self-id packet. 000 - node does not need power and does not repeat power 001 - node is self-powered and provides a minimum of 15 w to the bus 010 - node is self-powered and provides a minimum of 30 w to the bus. 011 - node is self-powered and provides a minimum of 45 w to the bus 100 - node may be powered from the b us and is using up to 1 w. 101 - node is powered from the bus and is using up to 1 w. an additional 2 w is needed to enable the link and higher layers. 110 - node is powered form the bus and is usi ng up to 1 w. an additional 5 w is needed to enable the link and higher layers. 111 - node is powered from the bus and is using up to 1 w. an additional 9 w is needed to enable the link and higher layers. jitter 3 r 0 the difference between the fastest and slowest repeater data delay, expressed as (jitter+1)*20ns resume_int 1 rw 0 resume interrupt enable. when set to one, the phy shall set port_event to one if resume operations commence for any port. isbr 1 rw 0 initiate short (arbitrated) bus reset. a write of one to this bit instructs the phy to arbitrate and issue a short bus reset. this bit is self-clearing. loop 1 rw 0 loop detect. a write of one to this bit clears it to zero. pwr_fail 1 rw 0 cable power failure detect. set to one when the ps bit changes from one to zero. a write of one to this bit clears it to zero. timeout 1 rw 0 arbitration state machine timeout. a write of one to this bit clears it to zero. port_event 1 rw 0 port event detect. the phy sets this bit to one if any of connected, bias, disabled or fault change for a port whose int_enable bit is one. the phy also sets this bit to one if resume www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 11 operations commence for any port and resume_int is one. a write of one to this bit clears it to zero. enab_accel 1 rw 0 enable arbitration acceleration. when set to one, the phy shall use the enhancements specification in p1394a. enab_multi 1 rw 0 enable multi-speed packet concatenation. when set to one, the link shall signal the speed of all packets to the phy. page_select 3 rw 000 selects which of eight possible phy register pages are accessible through the window at phy register address 1000b through 1111b, inclusive. port_select 4 rw 0000 if the page selected by page_select presents per port information, this field selects which port ? s registers are accessible through the window at phy register addressed 1000b through 1111b, inclusive. 7.3.phy register page0: port status page the port status page is used to access configuration and status information for each of the phy ? s port. the port is selected by writing zero to page_select and the desired port number to port_select in the phy register at address 0111. 0 1 2 3 4 5 6 7 1000b astat bstat child connected bias disabled 1001b negotiated_speed int_enable fault 1010b 1011b 1100b 1101b 1110b 1111b www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 12 7.4 phy register port status page fields size type power reset value description astat 2 r - tpa line state for the port 00 = invalid 01 =1 10 =0 11 =z bstat 2 r - (same encoding as astat) child 1 r - if equal to one, the port is a child, else a parent. the meaning of this bit is undefined from the time a bus reset is detected until the phy transitions to state t1:child handshake during the tree identify process(see 4.4.2.2 in ieee std 1394-1995) conncted 1 r 0 if equal to one, the port is connected, else disconnected. the value reported by this bit is filtered by hysteresis logic to reduce multiple status changes caused by contact scrape when a connector is inserted or removed. bias 1 r - if equal to one, bias voltage is detected( possible connection). the value reported by this bit is filtered by hysteresis logic to reduce multiple status changes caused by contact scrape when a connector is inserted or removed. disabled 1 rw 0 when set to one, the port shall be disabled. the value of this bit subsequent to a power reset is implementation- dependent, but should be a strappable option. negotiated_ speed 3 r - indicated the maximum speed negotiated between this phy port and its immediately connected port; the encoding is 000 ? 98.304mbit/s 001 ? 98.304 and 196.608 mbit/s 010 ? 98.304, 196.608 and 393.216 mbit/s int_enable 1 rw 0 enable port event interrupts. when set to one, the phy shall set port_event to one if any of connected, bias, disabled or fault (for this port) change state. fault 1 rw 0 set to one if an error is detected during a suspend or www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 13 resume operation. a write of one to this bit clears it to zero. 7.5 phy register page 1: vendor identification page the vendor identification page is used to identify the phy ? s vendor and compliance level. the page is selected by writing one to page_select in the phy register at address 0111. 0 1 2 3 4 5 6 7 1000b compliance_level 1001b reserved 1010b 1011b 1100b vendor_id 1101b 1110b 1111b product_id 7.6 phy register vendor identification page fields size type description compliance _level 8 r standard to which the phy implementation complies: 0 = not specified 1 = ieee p1394a all other values reserved for future standardization. the default is ? 1 ? . vendor_id 24 r the company id or organizationally unique identifier (oui) of the manufacturer of the phy. the most significant byte of vendor_id appears at phy register location 1010 and the least significant at 1100. the default value is ? 00 e0 4c ? . product_id 24 r the meaning of this number is determined by the company or organization that has been granted vendor_id. the most significant byte of product_id appears at phy register location 1101 and the least significant at 1111. the default value is ? 88 01 00 ? . www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 14 8.0 application information RTL8801 lreq dvss ctl0 ctl1 d0 d1 dvdd d3 d4 d5 d6 d7 dvss lact lps d2 dvdd lkon/c pdisable pc0 pc1 pc2 iso\ dxvss dxvdd test2 test1 agnd tvdd rvdd rgnd cps tpbias3 tpa3+ tpa3- tpb3+ tpb3- pvdd tpbias2 tpa2- tpb2+ tpb2- tpbias1 tpa1+ tpa1- tpb1+ tpb1- tpa2+ dvss sclk dvdd reset\ xo xi adgnd pllgnd btset bgnd tgnd pllgnd pllvdd bvdd pgnd advdd llc vdd 0.1uf 12 pf 12 pf vdd vdd vdd 4.7k ohm llc llc llc llc llc llc llc llc llc llc llc vdd link act llc or vdd vdd bus manager 10k ohm lkon pdisable power class power class power class iso vdd 390k ohm 68k ohm cable power vdd vdd vdd tpbias 1 tpbias2 tpbias 3 tp cable 3 tp cable 2 tp cable 1 www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 15 9. electrical characteristics 9.1 d.c. electric characteristics 9.1.1. absolute maximum ratings symbol conditions min. type. max. supply voltage -0.3v 4v storage temp. -65 j 150 j 9.1.2. operating conditions symbol conditions min. type. max. vcc supply voltage 3.0v 3.6 ta operating temperature 0 j 70 j 9.1.3. power dissipation max = 900 mw 9.2 a.c. electric characteristics a.c. timing 9.2.1. dn, ctln, lreq input setup and hold timing waveforms symbol parameter min type. max. units tsu setup time, dn, ctln, lreq to sysclk 5 ns th hold time, dn, ctln, lreq before sysclk 2 ns th tsu sysclk dn, ctln, lreq www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 16 note: 1.to be determined at seating plane -c- 2.dimensions d 1 and e 1 do not include mold symbol dimension in inch dimension in mm protrusion. d 1 and e 1 are maximum plastic body min nom max min nom max size dimensions including mold mismatch. a - - 0.067 - - 1.70 3.dimension b does not include dambar protrusion. a 1 0.000 0.004 0.008 0.00 0.1 0.20 dambar can not be located on the lower radius of the foot. a 2 0.051 0.055 0.059 1.30 1.40 1.50 4.exact shape of each corner is optional. b 0.006 0.009 0.011 0. 15 0.22 0.29 5.these dimensions apply to the flat section of the lead b 1 0.006 0.008 0.010 0.15 0.20 0.25 between 0.10 mm and 0.25 mm from the lead tip. c 0.004 - 0.008 0.09 - 0.20 6. a 1 is defined as the distance from the seating plane c 1 0.004 - 0.006 0.09 - 0.16 to the lowest point of the package body. d 0.472 bsc 12.00 bsc 7.controlling dimension : millimeter. d 1 0.394 bsc 10.00 bsc 8. reference document : jedec ms-026 , bbc e 0.472 bsc 12.00 bsc title : 64ld lqfp ( 10 x 10 x1.4mm) e 1 0.394 bsc 10.00 bsc package outline drawing , footprint 2.0mm www.datasheet.co.kr datasheet pdf - http://www..net/
RTL8801-ver. k datasheet 2002,7,1 17 e 0.020 bsc 0.50 bsc leadframe material: l 0.016 0.024 0.031 0.40 0.60 0.80 approve doc. no. l 1 0.039 ref 1.00 ref version 1 q 0 3.5 9 0 3.5 9 page of q 1 0 - - 0 - - check dwg no. lq064 - p1 q 2 12 typ 12 typ date nov. 06.1997 q 3 12 typ 12 typ realtek semi-conductor co., ltd realtek semiconductor co., ltd. reserved all rights of this document. no part of this document may be copied or reproduced in any form or by any means or transferred to any third party without the prior written consent of realtek semiconductor co., ltd. realtek reserves the right to change products or specifications without notice. this document has been carefully checked and is believed to be accurate. however realtek semiconductor co., ltd. assumes no responsibility for inaccuracies. www.datasheet.co.kr datasheet pdf - http://www..net/

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